Lim HH, Chua KL. Design of 32-Bit RISC-V Architecture Using Verilog Hardware Description Language. EEEE [Internet]. 2025 Oct. 28 [cited 2026 Aug. 15];6(2):465-76. Available from: https://periodical.uthm.edu.my/index.php/eeee/article/view/21260